1. Field of the Invention
This invention is concerned with clocked systems which use a clock to measure time intervals.
2. Description of the Related Art
Many electronic systems and products require that time intervals be measured with high precision. This is typically accomplished using a high frequency, high accuracy oscillator to provide a clock signal to the system. The period of the clock signal establishes a time unit which the system can use to define or measure time intervals.
Such a system typically needs to have a continuous clock running for timing purposes, and the high frequency oscillator and its accompanying buffer can consume a considerable amount of current. In a system where power consumption is a key issue, such as a portable telephone, the continuous running of such a clock can quickly and undesirably deplete the battery.
There may be times when activity levels in the system are low, and the only requirement of the high frequency clock is to facilitate the activation of certain functions at a later point in time. During such a period, it may be advantageous from a power consumption standpoint to disable the high frequency clock, and to employ a lower frequency, less accurate, and lower power clock to measure time intervalsxe2x80x94resulting in lower system power consumption. Unfortunately, the system may require such intervals to be timed as accurately as if the high frequency, high accuracy clock were still employed, which is generally not possible with the lower accuracy low frequency clock. A need exists for a system which allows the high frequency clock used to measure time intervals to be temporarily disabled, and while the high frequency clock is disabled, to employ a lower frequency, low power clock to measure time intervals with little to no loss of timing accuracy.
An asynchronous timing oscillator re-synchronizer system and method for use with a clocked system which uses a high frequency clock to measure time intervals is presented, which enables the clocked system to re-synchronize to the high frequency clock after it has been temporarily disabled. The re-synchronizer uses a low frequency, low power clock to determine the number of high frequency clock cycles that would have occurred during such intervals, with little to no loss of accuracy and with overall system power consumption reduced.
The invention is applicable to clocked systems which use a high frequency clock to measure time intervals. Both high frequency and low frequency clocks are provided to the re-synchronizer. A ratio between the frequencies of the high and low frequency clocks is determined and stored; the ratio is preferably periodically updated to correct for drift.
To disable the high frequency clock, a command is sent to the re-synchronizer which indicates that the high frequency clock is to be disabled for a specified number of cycles of the low frequency clock, referred to herein as the xe2x80x9cdisablement periodxe2x80x9d. Disablement typically occurs during periods of low activity, to reduce the system""s power consumption. In response to the disable command, a xe2x80x9cclock-disable counterxe2x80x9d causes the high frequency clock to be disabled, and begins counting low frequency clock cycles. When the disablement period has expired, the high frequency clock is re-enabled.
While the high frequency clock is disabled, a xe2x80x9cmissing high frequency clock cycles registerxe2x80x9d periodically increments the value stored in its register by the stored clock ratio, such that when the high frequency clock is re-enabled, the number in the missing high frequency clock cycles register represents the number of high frequency clock cycles that would have occurred during the disablement period. This number is provided to the clocked system, which can use it to adjust the timing in the system by adding in the cycles that were missed, thereby re-synchronizing the clocked system to the high frequency clock. Because the clock ratio is periodically updated to insure its accuracy, the number in the missing high frequency clock cycles register will accurately reflect the number of missed high frequency clock cycles, so that the use of the low frequency, low power clock during disablement periods incurs little to no loss of timing accuracy.
The high frequency clock typically includes an oscillator and a buffer which, when enabled, makes the oscillator output available to the clocked system. The high frequency clock can be disabled by disabling the oscillator, the buffer, or both. The oscillator is typically disabled by powering it down; when the oscillator is re-powered after having been powered down, a small amount of time is required for its frequency to stabilize. When configured to disable the high frequency clock by powering down the oscillator, the re-synchronizer preferably includes a stable time register, which stores the number of low frequency clock cycles required for the high frequency oscillator to stabilize. Using this number, the re-synchronizer re-enables the high frequency clock""s oscillator prior to the expiration of the disablement period such that the oscillator is stable and ready to use at the end of the disablement period. The re-synchronizer can also be configured to disable only the buffer, with the oscillator allowed to run continuously; in this case, no stable time register is required. An external means of re-enabling the high frequency clock prior to the end of the requested disable time may also be provided.